1. Technical Field
Embodiments of the disclosed invention are directed to a wafer level package for a semiconductor device, and in particular, to a land grid array package with improved thermal management.
2. Description of the Related Art
For manufacturers of semiconductor devices, there is a continuing pressure to increase the density and reduce the size of the devices, so that more devices can be made on a single wafer of semiconductor material, and so that products that incorporate the devices can be made more compact. One response to this pressure has been the development of chip scale and wafer level packaging. These are packages that have a footprint that is very close to the actual area of the semiconductor die. They are generally direct surface mountable, using, e.g., ball grid arrays (BGA) and flip chip configurations.
A land grid array (LGA) package is similar to a BGA package, in that contact pads are provided on the surface of the package at a pitch that is compatible with contacts of a particular circuit board design, but where the contacts on a BGA package are configured to receive solder balls, the contact pads of an LGA package are planar, configured to make full contact with the contacts on the circuit board. A very small volume of solder, relative to the volume of a solder ball of a comparable BGA, is used to couple each contact to the circuit board. Thus, an LGA package lies much closer to the circuit board than a BGA package.
Another development is the reconstituted wafer, in which a semiconductor wafer is separated into individual dice, which are spaced some greater distance apart than on the original wafer and embedded in a layer of molding compound to form the reconfigured wafer. A redistribution layer is formed over the dice to relocate contact points on the new wafer. One benefit is that this provides increased area for each die for “back end” processes, such as the formation of contacts at a scale or pitch that is compatible with circuit board limitations, without sacrificing valuable real estate on the original wafer. Such packages are typically referred to as fan-out wafer level packages (FWLP), because the contact positions of the original die are “fanned out” to a larger foot print.